Very Large Scale Integrated Circuits are being scaled to smaller dimensions to gain greater packing density and faster speed in a continuation of the trend of the past thirty years. Currently, CMOS technology is being manufactured with sub-100 nanometer (nm) minimum dimensions in 2005. Scaling CMOS with the minimum line width below 100 nm presents numerous problems to designers of integrated circuits. A few of the problems of the scaled CMOS transistors below 100 nm are highlighted below;                1. Power dissipation in CMOS is a big problem due to the high switching load caused by the increase in gate capacitance per unit area as the thickness of the gate dielectric is scaled.        2. The thickness of the gate dielectric used in the MOS transistor has been scaled down to less than 20 angstroms. Thinning of the gate dielectric has resulted in a significant amount of current through the gate dielectric as voltage is applied to the gate electrode. This current is termed the gate leakage.        3. The transistors conduct a finite current between the drain and source even when the gate voltage is reduced to zero. This current is termed the source drain leakage.        4. The result of the effects described above is CMOS circuits which conduct a significant amount of current even when there is no activity (static current); this undermines a key advantage of CMOS. Because of the static current, the static power, or the power dissipated by the CMOS chip when there is no activity, has become quite large, and at temperatures close to 100 degrees centigrade, the static power dissipation can become nearly equal to the dynamic power dissipation in CMOS circuits. As the CMOS technology is scaled to 65 nm, the problem of leakage is becoming more severe. This trend continues as the technology is scaled further to line widths of 45 nm and below.        5. The lateral scaling of CMOS design rules has not been accompanied by vertical scaling of feature sizes, resulting in three dimensional structures with extreme aspect ratios. For instance, the height of the polysilicon gate has decreased only 50% while the lateral dimension of the polysilicon gate has been reduced by over 90%. Dimensions of the “spacer” (a component of a CMOS transistor which separates the gate from the heavily doped source and drain regions) are dependent upon the height of the polysilicon, so it does not scale in proportion to the lateral dimensions. Process steps which are becoming difficult with scaling of vertical dimensions include formation of shallow source and drain regions, their silicidation without causing junction leakage, and etching and filling of contact holes to the source and drain regions.        6. It is well known to those skilled in the art to measure power supply leakage current as an effective screen for detecting defects introduced in the fabrication of the device. This method is sometimes referred to as the Iddq test by those skilled in the art. This method is effective for CMOS with the minimum line width above 350 nm. Scaling CMOS with the minimum line width below 350 nm increases the inherent leakage current to levels comparable to defect induced leakage current, rendering the Iddq test ineffective. Biasing the well voltage of the MOS device to eliminate the inherent leakage current introduces new elements of leakage such as gate leakage, junction tunneling leakage, etc.        
The prior art in junction field effect transistors dates back to the 1950s when they were first reported. Since then, they have been covered in numerous texts such as “Physics of Semiconductor Devices” by Simon Sze and “Physics and Technology of Semiconductor Devices” by Andy Grove. Junction field effect devices were reported in both elemental and compound semiconductors. Numerous circuits with junction field effect transistors have been reported, as follows;
such as:    Nanver and Goudena, “Design considerations for Integrated High-Frequency p-Channel p-JFETs”, IEEE Transactions Electron Devices, vol. 35, No. 11, 1988, pp. 1924-1933.    O. Ozawa, “Electrical Properties of a Triode Like Silicon Vertical Channel JFET”, IEEE Transcations Electron Devices, vol. ED-27, No. 11, 1980, pp. 2115-2123.    H. Takanagi and G. Kano, “Complementary JFET Negative-Resistance Devices”, IEEE Journal of Solid State Circuits, vol. SC-10, No. 6, December 1975, pp. 509-515.    A. Hamade and J. Albarran, “A JFET/Bipolar Eight-Channel Analog Multiplexer”, IEEE Journal of Solid State Circuits, vol. SC-16, No. 6, December 1978.    K. Lehovec and R. Zuleeg, “Analysis of GaAs FET's for Integrated Logic”, IEEE Transaction on Electron Devices, vol. ED-27, No. 6, June 1980.
In addition, a report published by R. Zuleeg titled “Complementary GaAs Logic”, dated 4 Aug., 1985 is cited as prior art. The authors have also published the material in Electron Device Letters in 1984 in a paper titled “Double Implanted GaAs Complementary JFETS”.
A representative structure of a conventional n-channel JFET is shown in FIG. 8. The JFET is formed in an n-type substrate 810. It is contained in a p-well region marked 815. The body of the JFET is shown as 820, which is an n-type diffused region containing source (832), channel (838), and drain (834) regions. The gate region (836) is p-type, formed by diffusion into the substrate. Contacts to the source, drain, and gate regions are marked as 841, 842, and 840, respectively. The critical dimension of the JFET is the gate length, marked as 855. It is determined by the minimum contact hole dimension 850, plus the necessary overlap required to ensure that the gate region encloses the gate contact. The gate length 855 is significantly larger than 850. This feature of construction of the prior art JFET limits the performance of these devices, since channel length is substantially larger than the minimum feature size. In addition, the capacitances of the vertical sidewalls of the gate diffusion to drain and source regions 861 and 862 respectively are also quite large. The gate-drain sidewall capacitance forms the Miller capacitance, a term known to those skilled in the art, and significantly limits the performance of the device at high frequencies.
Accordingly, it is desirable to have an integrated circuit and device structure as well as a method for fabrication to address the above mentioned problems as the geometry continues to scale down. Optionally, it is also desirable to fabricate this new integrated circuit and device structure using a method similar to that for fabricating CMOS devices to take advantage of the existing facility and equipment infrastructure.